1. Field of the Invention
The present invention generally relates to integrated circuit devices and, more particularly to buffer circuits utilized in integrated circuit devices.
2. Description of the Related Art
Integrated circuit devices (ICs) utilize input buffers for a variety of purposes, such as receiving input signals supplied from an external device and supplying a “buffered version” of the input signals to some other portion of the IC for processing. As illustrated in FIG. 1, a conventional input buffer 100 typically utilizes two stages: a differential amplifier stage 110 and a simple inverter stage 120.
The differential amplifier stage 110 typically receives an input signal (VIN) applied to one input and a reference voltage (VREF) applied to another input. As illustrated, the differential amplifier stage 110 includes an arrangement of PMOS transistors (MPA and MPB) and NMOS transistors (MNA, MNB, and MNE). The differential amplifier stage 110 generates a single ended output VDA that basically represents an amplification of the difference between VREF and VIN when the circuit is enabled (via MNE). In other words, if the voltage level of VREF is greater than VIN, more current will flow through MNA than MNB and the potential at output node B will be high. On the other hand, if the voltage level of VREF is less than VIN, more current will flow through MNB than MNA and the potential at output node B will be low.
The inverter stage 120 receives the single ended output signal VDA generated on output node B as an input and generates a corresponding output signal VOUT. As VDA transitions high, MN1 is turned on and MP1 is turned off. Therefore, the output node NO is pulled low as current IN1 flows through MN1, thus resulting in a logic high for VOUT at the output of output inverter 122. As VDA transitions low, MN1 is turned off and MP1 is turned on. Therefore, the output node NO is pulled high as current IN1 flows through MN1, thus resulting in a logic low for VOUT at the output of output inverter 122.
Thus, the main purpose of the inverter stage 120 is to transfer VDA to the next stage, preferably with little difference (or “skew”) between rising and falling edges. By tuning the size of the transistors used in the inverter stage 120 to match the rate at which the output node is discharged or precharged (as current IN1 and IP1 flows, respectively), the skew between rising and falling edges can be minimized. However, current flow through NMOS and PMOS transistors is highly sensitive to process variations (e.g., variations in supply voltages or operating temperature).
As illustrated in FIG. 2A, process variations resulting in stronger NMOS current drive (relative to PMOS current drive) may result in node NO being pulled down through MN1 faster than it is pulled up through MP1 (resulting, e.g., in a faster discharge rate). Similarly, as illustrated in FIG. 2B, process variations resulting in weaker NMOS current drive may result in node NO being pulled down through MN1 slower than it is pulled up through MP1 (resulting, e.g., in a faster precharge rate). Either case results in a skew between rise and fall times which must be accounted for in the specified setup/hold time of the input buffer 100. As device frequencies increase, it is essential to minimize such skew.
Accordingly, there is a need for an improved buffer circuit that is less sensitive to process variations than conventional buffer circuits.